In Progress

Features + Specifications:

2. ~1-24V input voltage (for safe operation at 1.5A)
3. Reverse polarity protection
4. Current sense terminals (1mV= 1mA)

Design Details:

1. The design is relatively straightforward. My implementation is largely based off of the below circuit, which was a user contribution on the EEVBlog forum:
2. The theory of  operation is as follows:
1. A 5V regulator produces a stable reference voltage.
2. The 5V reference is applied to the front panel potentiometer. The potentiometer forms a voltage divider which can produce any voltage between 0 and 5V.
3. The divided voltage is fed into an op-amp buffer (U1A).
4. The buffered voltage is divided down again via a 24K and 10K resistor (R11 and R12 in the schematic). These two resistors effectively set the maximum current the load can sink.
5. This new voltage is applied to the inverting terminal of an op-amp error amplifier (U1C). Remember, an op-amp (with feedback) will constantly adjust its output to keep the difference between its inputs zero. In this case, U1C tries to keep the voltage across the 1Ω sense resistor (10 x 10Ω resistors in parallel) exactly equal to the voltage on its inverting terminal.
6. So, if we apply 1V to the inverting terminal, then U1C will try to maintain 1V across the 1Ω resistor as well. If there is 1V across a 1Ω resistor, then by Ohm’ Law, we know there must be a current of 1A.
7. Here, MOSFET Q1 is operated in its “ohmic region”. Essentially, it acts like a voltage controlled resistor. Depending on the desired current, U1C adjusts the gate-source voltage of Q1 to turn it more on, or more off.
8. Notice some of the loop-compensation components around U1C/Q1. C4 essentially sets the bandwidth of the control loop. R15 limits the dV/dt on the gate, which affects the transient response of the load. Lower resistance usually coincides with more overshoot/ringing on a load-step.